Instruction Cycle
and Instruction Formatting

last updated 11/25/01

loop forever

   fetch instruction whose address is in PC

   update the PC

   decode the instruction

   fetch operand(s)

   execute instruction

   store result

end loop

Note the early timing of the PC update. The PC is always pointing to the next instruction, even at this level of analysis.

Implementing the Instruction Cycle

Much of the execution of the instruction cycle is accomplished by transferring data between registers and activating ALU or memory circuits.

Two approaches of implementation commonly used are "hard-wiring" and "micro-programming".

"hard-wire"

control the timing of each sub-step or register transfer by clock pulses, counters and other logic specific to each instruction
technique was used in early machines (first and second generation)
typically faster than micro-programming
used again in today's RISC (Reduced Instruction Set Computers)

"micro-program"

recognizing that instruction execution is implemented by sequencing the transfer (input and output) of registers in the CPU and activation of ALU components, those steps are just like programming.
The pseudocode shown above for the instruction cycle is much like the microprogram.
now you need a microprogram instruction cycle which is then hard wired

Instruction format

The instruction format encodes

operation
type of operands
operands consisting of registers, memory addresses and mode of the operand

The instruction format is specific to each machine. This is why you cannot take program binaries for one machine and run them on different platforms.

Complex machines ("CISC" , e.g., VAX) have a variety of instruction formats for a large number of instructions and instruction groups. This makes decoding more difficult and possibly more time intensive.

RISC's greatly simplify the instruction format for easy and fast decoding, hence the name "reduced instruction set computers"

Example Instruction Format

32 bit words

fixed fields

assume at most one memory reference per instruction as in GAL

Opcode Assignments (bits 31-28)

0000 -	halt	1000	- add
0001 -	copy	1001	- sub
0010 -	load_address	1010	- mult
0011 -	trap	1011	- divide
0100 -	jump	1100	- and
0101 -	compare	1101	- or
0110 -	jump.sub	1110	- not
0111 -	Return	1111	- rotate

Remaining fields

Size (bits 27-24)

0000 - byte
0001 - word
0010 - longword

Mode codes

bit 23 : 0=direct, 1=indirect
bit 22 : 0=not immediate, 1=immediate
bit 21 : 0=reg is destination, 1=reg is source
bit 20 : 0=no RAM operands

Register codes (bits 19-16)

2⁴ = 16 registers

RAM address (bits 15-0)
also doubles for immediate values,
or second register reference.

Typically displacement offsets, rather than a hard ram addresses, are stored here.

Sample encodings


add.int    r4,total
copy.int   #2,r5
copy.char  (r2),r6
divide.int r3,r5
jump       label
return

Instruction Cycle and Instruction Formatting