last updated 11/25/01
Executing the AND operation on registers X and Y.
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x |
y |
Carry |
Sum |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
Half Adder
Must add in the carry bit of previous sum
x |
y |
cI |
Carry |
Sum |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
8 bit addition using full adders

What simple modification of the above would allow for an ADD with Carry (ADWC) instruction?
We want to compute X-Y
Following is the modification to an adder circuit to implement subtraction. Shown is the circuit on the outputs of only one of the bits on the Y register. The line from the right is the control line from the control unit of the CPU to the ALU that the add operation is either an add or subtract. The 2-AND-OR-NOT gate combination is a classic circuit to select one of two inputs as the output.
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Multiplication circuits are typically built of adders, shifters. Also need control circuits
There are many techniques to perform multiplication
Some simple analyses on multiplication
Example
25 (MULTIPLICAND or "Q") x 13 (MULTIPLIER or "M") = 25 + 25 + 25 + ... + 25 (13 times) = 325 (PRODUCT or "P")
Analysis
Check out the subroutine MULT1 which performs repeat addition multiplication.
Example
25 x 13 75 = 25+25+25 25 = 250 (25 shifted one digit place) 325
Analysis and observations
25 x 13 +75 7:5 shift partial product to right +25 32:5
In a binary number system context
11001 x 1101 11001 add 00000 shift Q, no add 11001 shift Q, add 11001 shift Q, add 101000101
11001
x 1101
+11001 add
>>11001 shift P
+00000 no add
11001
>> 11001 shift P
+11001 add
1111101
>>1111101 shift
+11001 add
101000101
Check out the subroutine MULT2 which performs shift and add multiplication.
Want to treat positive and negative multipliers uniformly, i.e., no sign analysis
Want to performs fewer additions (and subtractions) than in add/shift algorithm if possible
Idea:
Example
28 = 32-8+4 = 25- 23+22 = 0 0 1 0 -1 1 0 0
Also 28 = 32-4 = 25 -22= 0 0 1 0 0 -1 0 0
Signed number systems are redundant.
Negative numbers
negate the one's in the positive representation
Scan right to left analyzing each pair of bits
00 -> 0 01 -> 1 10 -> -1 11 -> 0
Example
28 = 00011100.0 = 0 0 1 0 0 -1 0 0
-28 = 11100100.0 = 0 0 -1 0 1 -1 0 0
So 10 x 28 looks like:
0 1 0 1 0
0 0 1 0 0 -1 0 0
+ 0 0 0 0 0
shift> 0 0 0 0 0 : 0
+ 0 0 0 0 0
0 0 0 0 0 : 0
shift> 0 0 0 0 0 : 0 0
- 0 1 0 1 0
1 0 1 1 0 : 0 0
shift> 1 1 0 1 1 : 0 0 0
+ 0 0 0 0 0
1 1 0 1 1 : 0 0 0
shift> 1 1 1 0 1 : 1 0 0 0
+ 0 0 0 0 0
1 1 1 0 1 : 1 0 0 0
shift> 1 1 1 1 0 : 1 1 0 0 0
+ 0 1 0 1 0
0 1 0 0 0 : 1 1 0 0 0
only shifts are left. The above is binary for 280
Modification of shift and add
Scan M right to left and analyze bit pairs instead of the single bit:
Check out the subroutine MULT3 which performs Booth's algorithm.
Take into account that immediately adjacent addition and subtraction pair can be replaced by one operation
Example
Now look at triples of bits instead of pairs (two pairs transform to one triple). Accounting for the shift that occurs, in the original algorithm:
00 -> Shift 01 -> Add then Shift 10 -> Sub then Shift 11 -> Shift
Replace with
000 -> Shift, Shift 001 -> Add, Shift, Shift 010 -> Add, Shift, Shift 011 -> Shift, Add, Shift 100 -> Shift, Sub, Shift 101 -> 110 -> 111 ->
Check out the subroutine MULT4 which performs Booth's modified algorithm.
Division is repeat subtraction. Unfortunately, since division is not commutative there are few algorithms to efficiently perform subtraction.
Decimal example
021 R1
13)274
26
14
13
1
Binary example
000010101 R1
1101)100010010
1101
10000
1101
1110
1101
1
Shift next digit from dividend for subtraction
Subtract divisor from dividend'
If difference > 0 then set quotient bit
else clear quotient bit and add divisor back (restore) into dividend'
Repeat until all digits are shifted
Division is the inverse of multiplication.
Begin with double word dividend and a single word divisor.
Result in single word quotient and single word remainder. Note that overflow is possible.
As dividend shrinks (shifted) the quotient grows so that the dividend and quotient can share the register pair.
R0 R1 0 0 0 1|0 1 0 0 initial 0 0 1 0|1 0 0: shift (1) 0 0 1 0|1 0 0:0 sub/restore (1) 0 1 0 1|0 0:0 shift(2) 0 0 1 0|0 0:0 1 sub/set (2) 0 1 0 0|0:0 1 shift(3) 0 0 0 1|0:0 1 1 sub/set (3) 0 0 1 0:0 1 1 shift(4) 0 0 1 0:0 1 1 0 sub/restore (4) remainder:quotient
Check out the subroutine RESDIV which performs restoring division.
Improvement: really don't need to restore quotient; instead, keep shifting and add rather than subtract.
Only when sub/add operation results in a positive dividend do we set quotient bit and switch back to subtract.
Sequence of operations in original algorithm in the loop after subtraction:
Working through the example
R0 R1
0 0 0 1|0 1 0 0 initial
0 0 1 0|1 0 0: shift (1)
1 1 1 1|1 0 0:0 sub/clear (1)
1 1 1 1|0 0:0 shift(2)
0 0 1 0|0 0:0 1 add/set (2)
0 1 0 0|0:0 1 shift(3)
0 0 0 1|0:0 1 1 sub/set (3)
0 0 1 0:0 1 1 shift(4)
1 1 1 1:0 1 1 0 sub/clear (4)
0 0 1 0:0 1 1 0 restore negative remainder
remainder:quotient
Check out the subroutine NONDIV which performs nonrestoring division.